Projects & Achievements

Overview

AES-128/192/256 hardware accelerator for end-to-end encryption in edge devices. Makes use of a 32-bit iterative core along with a KeyGen Module. Our team designed the Data Path, Control Path, KeyGen and IO Controller Modules and implemented the same. Successful Encryption/Decryption was achieved on the Basys-3 FPGA with an operating frequency of 100 MHz. Back-end design was done in collaboration with Semi Conductor Laboratory, Chandigarh.

Technical Implementation

• Core Architecture: 32-bit iterative core with KeyGen module for AES-128/192/256
• Module Design: Data Path, Control Path, KeyGen, and IO Controller modules
• FPGA Prototyping: Successfully tested on Basys-3 FPGA at 100 MHz operating frequency
• Back-end Design: Collaborated with Semi Conductor Laboratory, Chandigarh for ASIC back-end flow

Key Contributions

• Designed the Data Path and Control Path modules
• Implemented and verified individual transformation blocks (S-Box, MixColumns, etc.)
• Conducted timing analysis and optimization to meet performance targets
• Developed comprehensive testbenches for functional verification

Overview

Designed and implemented a specialized cryptographic processor for Elliptic Curve Cryptography (ECC). Our team designed the core data path and control path modules for performing ECC operations with an Instruction Set Architecture using iterative resource sharing, similar to a microprocessor. A POC for Homomorphic extension of ECC was also developed.

Architecture Design

• Custom ISA: Designed instruction set to perform Point Addition and Point Doubling operations with iterative resource sharing
• Datapath Design: Implemented arithmetic units for finite field operations (addition, multiplication, inversion)
• Control Path: Designed control logic to orchestrate ECC algorithms
• Homomorphic Extension: Developed proof-of-concept for Homomorphic extension of ECC

Key Contributions

• Designed the core data path and control path modules
• Implemented ISA with iterative resource sharing concept
• Developed POC for Homomorphic extension of ECC
• Verified correctness against standard ECC test vectors

Overview

Developed an autonomous floating robot designed to accumulate surface waste from local water bodies, providing a cost-effective solution for environmental conservation. This project combines robotics, embedded systems programming, and environmental engineering.

Problem Statement

Local water bodies face significant pollution from floating debris and surface waste. Manual cleaning is labor-intensive and costly. This project aimed to create an automated, low-cost solution for continuous waste collection.

Technical Implementation

Hardware Design

• Platform: Designed floating platform with stability for water operation
• Collection Mechanism: Implemented mechanical system for waste capture and storage
• Motor Control: DC motors with PWM control for navigation
• Sensors: Ultrasonic and IR sensors for obstacle detection and navigation

Software Architecture

• Movement Algorithm: Designed algorithm for efficient coverage of testing area
• Obstacle Avoidance: Implemented real-time path planning to navigate around obstacles
• State Machine: Developed finite state machine for behavior control
• Power Management: Optimized for extended operation time

Key Contributions

• Played a crucial role in designing the movement algorithm for the testing environment
• Implemented embedded C code for Arduino microcontroller
• Developed sensor fusion for navigation and obstacle detection
• Conducted field testing and iterative improvements

Impact

This project demonstrates practical engineering skills applied to environmental problems, combining hardware design, embedded programming, and algorithm development to create a working prototype for water conservation.

Overview

Implemented hardware modules for the CLEFIA cryptographic algorithm, a block cipher designed for both software and hardware efficiency. This project focused on the Key Scheduling Algorithm (KSA) and critical arithmetic blocks required for the cipher operations.

About CLEFIA

CLEFIA is a 128-bit block cipher supporting key lengths of 128, 192, and 256 bits. Developed by Sony, it's designed for high security and efficiency across various platforms, from embedded devices to high-performance systems.

Technical Implementation

Key Scheduling Algorithm (KSA)

• Main Focus: Implemented complete key expansion logic
• Round Key Generation: Designed hardware to generate round keys from master key
• Optimization: Balanced area and timing for efficient FPGA implementation

Arithmetic Blocks

• S-Boxes: Implemented substitution boxes for non-linear transformation
• Diffusion Functions: Designed arithmetic blocks for data mixing (F-functions)
• XOR Networks: Implemented whitening key operations

Key Contributions

• Mainly worked on implementing the Key Scheduling Algorithm
• Designed and implemented several arithmetic blocks for core cipher operations
• Conducted functional verification and timing analysis
• Integrated modules into complete CLEFIA encryption system

Technical Skills Demonstrated

• Hardware description language (Verilog) proficiency
• Understanding of block cipher design principles
• FPGA synthesis and implementation using Xilinx ISE
• Cryptographic algorithm analysis and implementation